Field of the Invention
The present invention relates in general to voltage level translation, and more particularly to a low voltage to high voltage level translator that is independent of the high supply voltage.
Description of the Related Art
Level translators are used for translating low voltage logic signals to a higher voltage level. For example, a common application is to convert 3 Volt (V) logic signals to 5V logic signals. A conventional design works well when the low and high voltages are sufficiently close to each other, including the aforementioned example, in which the low to high translation ratio is not too low (meaning that the higher voltage is not significantly higher than the lower voltage). The conventional level translator design works best if the ratio of the low to high voltages is greater than 0.5. For ratios lower than 0.5, such as, for example, 0.2 (e.g., 1V to 5V) the conventional design becomes unwieldy when the voltage translator is implemented using field-effect transistors (FETs) because of the large values for channel width (W) and length (L) of the FETs.
Digital logic circuits are trending to lower and lower voltages, e.g., 2.5V, 1.8V, 1.5V, 1.2V, 1.0V, etc., in which voltage translation is generally made to the same higher voltage output. As the input voltage decreases, the FET gate areas increase resulting in a higher gate-source capacitance. The higher gate-source capacitance slows down the switching speed of the level translator. Another issue is that conventional designs are typically optimized only at a specific low voltage to high voltage ratio.